The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the Equality+LinearArith division in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 23392 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics:
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 22802 | 711710.853 | 711762.025 | 590 | 0 | 555 | 0 |
cvc5 | 0 | 21092 | 2515923.862 | 2513112.802 | 2300 | 0 | 1938 | 0 |
smtinterpol | 0 | 20564 | 3310552.733 | 3261088.495 | 2828 | 0 | 2625 | 0 |
veriT | 0 | 14668 | 632660.573 | 632572.547 | 541 | 8183 | 491 | 4 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 22802 | 711913.563 | 711734.185 | 590 | 0 | 555 | 0 |
cvc5 | 0 | 21092 | 2516298.332 | 2513019.762 | 2300 | 0 | 1938 | 0 |
smtinterpol | 0 | 20564 | 3513385.343 | 3220654.16 | 2828 | 0 | 2503 | 0 |
veriT | 0 | 14668 | 632737.433 | 632551.977 | 541 | 8183 | 491 | 4 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.