The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFLIRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 9888 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 9849 | 58453.907 | 58432.172 | 39 | 39 | 0 |
cvc5 | 0 | 9805 | 96615.874 | 96491.415 | 83 | 77 | 0 |
veriT | 0 | 9660 | 266387.593 | 266337.18 | 228 | 221 | 0 |
smtinterpol | 0 | 9536 | 373877.259 | 365209.916 | 352 | 296 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 9849 | 58460.827 | 58430.882 | 39 | 39 | 0 |
cvc5 | 0 | 9805 | 96631.434 | 96487.155 | 83 | 77 | 0 |
veriT | 0 | 9660 | 266402.983 | 266330.08 | 228 | 221 | 0 |
smtinterpol | 0 | 9536 | 389416.149 | 363396.801 | 352 | 288 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.