The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFDTLIRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 4977 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 4935 | 14224.631 | 14221.666 | 42 | 10 | 0 |
cvc5 | 0 | 4748 | 177164.331 | 176073.803 | 229 | 106 | 0 |
smtinterpol | 0 | 4525 | 463293.608 | 449621.544 | 452 | 354 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 4935 | 14229.301 | 14221.206 | 42 | 10 | 0 |
cvc5 | 0 | 4748 | 177179.981 | 176068.823 | 229 | 106 | 0 |
smtinterpol | 0 | 4525 | 466402.338 | 447823.533 | 452 | 348 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.