SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions

SMT-COMP 2022

Rules
Benchmarks
Tools
Specs
Proof Exhibition Track
Parallel & Cloud Tracks
Participants
Results
Statistics
Comparisons
Slides

AUFDTLIRA (Proof Exhibition Track)

Competition results for the AUFDTLIRA logic in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 4977
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 4935 14224.631 14221.6664210 0
cvc5 0 4748 177164.331 176073.803229106 0
smtinterpol 0 4525 463293.608 449621.544452354 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 493514229.30114221.2064210 0
cvc5 0 4748177179.981176068.823229106 0
smtinterpol 0 4525466402.338447823.533452348 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.