The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFIDL logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 57 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| cvc5-lfsc | 0 | 57 | 7.134 | 7.099 | 0 | 0 | 0 |
| cvc5 | 0 | 57 | 264.502 | 246.241 | 0 | 0 | 0 |
| veriT | 0 | 55 | 195.501 | 194.972 | 2 | 0 | 0 |
| smtinterpol | 0 | 54 | 4193.701 | 3997.586 | 3 | 3 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| cvc5-lfsc | 0 | 57 | 7.134 | 7.099 | 0 | 0 | 0 |
| cvc5 | 0 | 57 | 264.502 | 246.241 | 0 | 0 | 0 |
| veriT | 0 | 55 | 195.501 | 194.972 | 2 | 0 | 0 |
| smtinterpol | 0 | 54 | 4193.701 | 3997.586 | 3 | 3 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.