The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFDTLIA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 88 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
smtinterpol | 0 | 74 | 3089.813 | 2680.187 | 14 | 2 | 0 |
cvc5-lfsc | 0 | 60 | 37291.476 | 37269.27 | 28 | 28 | 0 |
cvc5 | 0 | 28 | 72111.774 | 72113.025 | 60 | 59 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
smtinterpol | 0 | 74 | 3089.813 | 2680.187 | 14 | 2 | 0 |
cvc5-lfsc | 0 | 60 | 37293.856 | 37268.07 | 28 | 28 | 0 |
cvc5 | 0 | 28 | 72121.884 | 72109.815 | 60 | 59 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.