The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the ALIA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 41 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 41 | 16.341 | 16.34 | 0 | 0 | 0 |
smtinterpol | 0 | 41 | 108.009 | 39.309 | 0 | 0 | 0 |
cvc5 | 0 | 35 | 1681.163 | 1628.941 | 6 | 0 | 0 |
veriT | 0 | 27 | 16801.492 | 16802.039 | 14 | 14 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 41 | 16.341 | 16.34 | 0 | 0 | 0 |
smtinterpol | 0 | 41 | 108.009 | 39.309 | 0 | 0 | 0 |
cvc5 | 0 | 35 | 1681.163 | 1628.941 | 6 | 0 | 0 |
veriT | 0 | 27 | 16801.832 | 16801.619 | 14 | 14 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.