The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the UFLRA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 10 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 10 | 0.585 | 0.575 | 0 | 0 | 0 |
veriT | 0 | 10 | 0.589 | 0.528 | 0 | 0 | 0 |
cvc5-lfsc | 0 | 10 | 0.702 | 0.701 | 0 | 0 | 0 |
smtinterpol | 0 | 10 | 9.139 | 4.633 | 0 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
veriT | 0 | 10 | 0.589 | 0.528 | 0 | 0 | 0 |
cvc5 | 0 | 10 | 0.585 | 0.575 | 0 | 0 | 0 |
cvc5-lfsc | 0 | 10 | 0.702 | 0.701 | 0 | 0 | 0 |
smtinterpol | 0 | 10 | 9.139 | 4.633 | 0 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.