SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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Proof Exhibition Track
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UFLRA (Proof Exhibition Track)

Competition results for the UFLRA logic in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 10
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5 0 10 0.585 0.57500 0
veriT 0 10 0.589 0.52800 0
cvc5-lfsc 0 10 0.702 0.70100 0
smtinterpol 0 10 9.139 4.63300 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
veriT 0 100.5890.52800 0
cvc5 0 100.5850.57500 0
cvc5-lfsc 0 100.7020.70100 0
smtinterpol 0 109.1394.63300 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.