UFDTLIRA (Proof Exhibition Track)

Competition results for the UFDTLIRA logic in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 2916
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Unsolved	Timeout	Memout
cvc5-lfsc	0	2911	2915.933	2913.575	5	2	0
cvc5	0	2898	10615.468	10348.305	18	4	0
smtinterpol	0	2773	181348.207	177337.358	143	141	0

Parallel Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Unsolved	Timeout	Memout
cvc5-lfsc	0	2911	2917.023	2913.485	5	2	0
cvc5	0	2898	10616.958	10348.065	18	4	0
smtinterpol	0	2773	202860.637	173893.696	143	130	0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.