The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFLIA logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 1296 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
veriT | 0 | 1174 | 141716.345 | 141745.366 | 122 | 105 | 3 |
cvc5-lfsc | 0 | 1169 | 159000.895 | 159056.013 | 127 | 127 | 0 |
cvc5 | 0 | 1169 | 159152.822 | 159156.884 | 127 | 127 | 0 |
smtinterpol | 0 | 1040 | 318176.363 | 304296.727 | 256 | 230 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
veriT | 0 | 1174 | 141748.735 | 141739.636 | 122 | 105 | 3 |
cvc5-lfsc | 0 | 1169 | 159048.675 | 159049.673 | 127 | 127 | 0 |
cvc5 | 0 | 1169 | 159203.582 | 159149.804 | 127 | 127 | 0 |
smtinterpol | 0 | 1040 | 336887.843 | 300499.219 | 256 | 219 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.