The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the Equality+LinearArith division in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 12406 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics:
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 11785 | 49179.473 | 48915.572 | 621 | 0 | 548 | 0 |
cvc5 | 0 | 10850 | 46914.156 | 46354.124 | 1556 | 0 | 1359 | 0 |
SMTInterpol | 0 | 10438 | 107762.586 | 76069.545 | 1968 | 0 | 1866 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 11785 | 49179.473 | 48915.572 | 621 | 0 | 548 | 0 |
cvc5 | 0 | 10850 | 46914.156 | 46354.124 | 1556 | 0 | 1359 | 0 |
SMTInterpol | 0 | 10438 | 107762.586 | 76069.545 | 1968 | 0 | 1844 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.