SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2023

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Model Validation Track
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AUFDTLIRA (Proof Exhibition Track)

Competition results for the AUFDTLIRA logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 2527
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 2473 2051.989 2043.0055415 0
cvc5 0 2364 14273.108 14000.22516373 0
SMTInterpol 0 2160 26141.122 16433.713367343 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 24732051.9892043.0055415 0
cvc5 0 236414273.10814000.22516373 0
SMTInterpol 0 216026141.12216433.713367342 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.