The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFDTLIRA logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 2527 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 2473 | 2051.989 | 2043.005 | 54 | 15 | 0 |
cvc5 | 0 | 2364 | 14273.108 | 14000.225 | 163 | 73 | 0 |
SMTInterpol | 0 | 2160 | 26141.122 | 16433.713 | 367 | 343 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 2473 | 2051.989 | 2043.005 | 54 | 15 | 0 |
cvc5 | 0 | 2364 | 14273.108 | 14000.225 | 163 | 73 | 0 |
SMTInterpol | 0 | 2160 | 26141.122 | 16433.713 | 367 | 342 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.