UFDTLIA (Proof Exhibition Track)

Competition results for the UFDTLIA logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 202
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Unsolved	Timeout	Memout
cvc5-lfsc	0	30	931.651	927.166	172	172	0
cvc5	0	30	1271.597	1243.314	172	172	0
SMTInterpol	0	20	2948.6	2559.438	182	182	0

Parallel Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Unsolved	Timeout	Memout
cvc5-lfsc	0	30	931.651	927.166	172	172	0
cvc5	0	30	1271.597	1243.314	172	172	0
SMTInterpol	0	20	2948.6	2559.438	182	182	0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.