UFDTLIRA (Proof Exhibition Track)

Competition results for the UFDTLIRA logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 1471
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Unsolved	Timeout	Memout
cvc5-lfsc	0	1462	280.647	274.33	9	2	0
cvc5	0	1457	3184.77	3089.069	14	5	0
SMTInterpol	0	1383	8093.75	4666.955	88	78	0

Parallel Performance

Solver	Error Score	Correct Score	CPU Time Score	Wall Time Score	Unsolved	Timeout	Memout
cvc5-lfsc	0	1462	280.647	274.33	9	2	0
cvc5	0	1457	3184.77	3089.069	14	5	0
SMTInterpol	0	1383	8093.75	4666.955	88	78	0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.