The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the AUFLIRA logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 4946 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 4938 | 7624.885 | 7613.841 | 8 | 8 | 0 |
cvc5 | 0 | 4907 | 2098.145 | 2075.633 | 39 | 38 | 0 |
SMTInterpol | 0 | 4749 | 16034.973 | 9118.599 | 197 | 197 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 4938 | 7624.885 | 7613.841 | 8 | 8 | 0 |
cvc5 | 0 | 4907 | 2098.145 | 2075.633 | 39 | 38 | 0 |
SMTInterpol | 0 | 4749 | 16034.973 | 9118.599 | 197 | 193 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.