SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions

SMT-COMP 2023

Rules
Benchmarks
Specs
Model Validation Track
Proof Exhibition Track
Parallel & Cloud Tracks
Participants
Results
Statistics
Comparisons
Slides

AUFLIRA (Proof Exhibition Track)

Competition results for the AUFLIRA logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 4946
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 4938 7624.885 7613.84188 0
cvc5 0 4907 2098.145 2075.6333938 0
SMTInterpol 0 4749 16034.973 9118.599197197 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 49387624.8857613.84188 0
cvc5 0 49072098.1452075.6333938 0
SMTInterpol 0 474916034.9739118.599197193 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.