The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFIDL logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 57 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 57 | 10.135 | 10.085 | 0 | 0 | 0 |
cvc5 | 0 | 55 | 310.576 | 307.188 | 2 | 0 | 0 |
SMTInterpol | 0 | 54 | 658.919 | 345.143 | 3 | 3 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 57 | 10.135 | 10.085 | 0 | 0 | 0 |
cvc5 | 0 | 55 | 310.576 | 307.188 | 2 | 0 | 0 |
SMTInterpol | 0 | 54 | 658.919 | 345.143 | 3 | 3 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.