SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2023

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Model Validation Track
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UFLIA (Proof Exhibition Track)

Competition results for the UFLIA logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 1986
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 1872 13679.627 13487.528114114 0
SMTInterpol 0 1225 29308.135 23314.363761758 0
cvc5 0 1151 12907.604 12789.965835776 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 187213679.62713487.528114114 0
SMTInterpol 0 122529308.13523314.363761754 0
cvc5 0 115112907.60412789.965835776 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.