SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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Proof Exhibition Track
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Equality (Proof Exhibition Track)

Competition results for the Equality division in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 2938
Time Limit: 1200 seconds
Memory Limit: 60 GB

Logics: This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedAbstainedTimeout Memout
cvc5-lfsc 0 2653 339658.231 339772.8162850270 0
cvc5 0 2616 389552.686 389544.163220307 0
smtinterpol 0 1632 1625150.434 1598594.715130601287 0
veriT 0 1594 218916.476 218950.211901154150 6

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedAbstainedTimeout Memout
cvc5-lfsc 0 2653339756.531339758.3462850270 0
cvc5 0 2616389655.896389527.383220307 0
smtinterpol 0 16322017720.1041521631.519130601060 0
veriT 0 1594218953.346218942.151901154150 6

n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.