The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFDT logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 1154 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 1048 | 129764.42 | 129803.267 | 106 | 105 | 0 |
cvc5-lfsc | 0 | 1035 | 129461.81 | 129506.933 | 119 | 104 | 0 |
smtinterpol | 0 | 673 | 591235.03 | 581152.113 | 481 | 470 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 1048 | 129805.66 | 129797.257 | 106 | 105 | 0 |
cvc5-lfsc | 0 | 1035 | 129502.19 | 129501.373 | 119 | 104 | 0 |
smtinterpol | 0 | 673 | 704388.85 | 559040.311 | 481 | 405 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.