The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UF logic in the Proof Exhibition Track.
Page generated on 2022-08-10 11:19:33 +0000
Benchmarks: 1784 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 1618 | 210196.421 | 210265.883 | 166 | 166 | 0 |
veriT | 0 | 1594 | 218916.476 | 218950.21 | 190 | 150 | 6 |
cvc5 | 0 | 1568 | 259788.266 | 259740.893 | 216 | 202 | 0 |
smtinterpol | 0 | 959 | 1033915.404 | 1017442.602 | 825 | 817 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 1618 | 210254.341 | 210256.973 | 166 | 166 | 0 |
veriT | 0 | 1594 | 218953.346 | 218942.15 | 190 | 150 | 6 |
cvc5 | 0 | 1568 | 259850.236 | 259730.123 | 216 | 202 | 0 |
smtinterpol | 0 | 959 | 1313331.254 | 962591.208 | 825 | 655 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.