SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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Proof Exhibition Track
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UF (Proof Exhibition Track)

Competition results for the UF logic in the Proof Exhibition Track.

Page generated on 2022-08-10 11:19:33 +0000

Benchmarks: 1784
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 1618 210196.421 210265.883166166 0
veriT 0 1594 218916.476 218950.21190150 6
cvc5 0 1568 259788.266 259740.893216202 0
smtinterpol 0 959 1033915.404 1017442.602825817 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 1618210254.341210256.973166166 0
veriT 0 1594218953.346218942.15190150 6
cvc5 0 1568259850.236259730.123216202 0
smtinterpol 0 9591313331.254962591.208825655 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.