The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the Equality division in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 1880 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics: This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 1411 | 11341.003 | 11328.052 | 469 | 0 | 461 | 0 |
cvc5 | 0 | 1390 | 11607.476 | 11570.962 | 490 | 0 | 474 | 0 |
SMTInterpol | 0 | 817 | 51523.264 | 37509.632 | 1063 | 0 | 1053 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 1411 | 11341.003 | 11328.052 | 469 | 0 | 461 | 0 |
cvc5 | 0 | 1390 | 11607.476 | 11570.962 | 490 | 0 | 474 | 0 |
SMTInterpol | 0 | 817 | 52037.354 | 37327.912 | 1063 | 0 | 1018 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.