SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2023

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Model Validation Track
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UFDT (Proof Exhibition Track)

Competition results for the UFDT logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 903
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5 0 593 4789.869 4785.781310302 0
cvc5-lfsc 0 593 5026.221 5020.331310302 0
SMTInterpol 0 349 19770.533 13578.779554543 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5 0 5934789.8694785.781310302 0
cvc5-lfsc 0 5935026.2215020.331310302 0
SMTInterpol 0 34919770.53313578.779554532 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.