The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFDT logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 903 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 593 | 4789.869 | 4785.781 | 310 | 302 | 0 |
cvc5-lfsc | 0 | 593 | 5026.221 | 5020.331 | 310 | 302 | 0 |
SMTInterpol | 0 | 349 | 19770.533 | 13578.779 | 554 | 543 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 593 | 4789.869 | 4785.781 | 310 | 302 | 0 |
cvc5-lfsc | 0 | 593 | 5026.221 | 5020.331 | 310 | 302 | 0 |
SMTInterpol | 0 | 349 | 19770.533 | 13578.779 | 554 | 532 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.