SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2023

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Model Validation Track
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UF (Proof Exhibition Track)

Competition results for the UF logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 977
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 818 6314.782 6307.722159159 0
cvc5 0 797 6817.607 6785.18180172 0
SMTInterpol 0 468 31752.731 23930.853509510 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 8186314.7826307.722159159 0
cvc5 0 7976817.6076785.18180172 0
SMTInterpol 0 46832266.82123749.133509486 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.