The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFDTNIA logic in the Incremental Track.
Page generated on 2022-08-10 11:18:22 +0000
Benchmarks: 139 Time Limit: 1200 seconds Memory Limit: 60 GB
Parallel Performance |
---|
cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 560 | 14027.686 | 14023.916 | 186 | 9 | 0 |
smtinterpol | 0 | 0 | 69.3 | 73.752 | 746 | 0 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 563.118 | 243.673 | 746 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.