The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the QF_UFLRA logic in the Model Validation Track.
Page generated on 2022-08-10 11:19:11 +0000
Benchmarks: 385 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
Yices2 | smtinterpol |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Yices2 | 0 | 382 | 3630.391 | 3632.978 | 3 | 0 |
smtinterpol | 0 | 382 | 4320.568 | 3261.826 | 2 | 0 |
2021-SMTInterpoln | 0 | 382 | 4478.692 | 3256.564 | 2 | 0 |
OpenSMT | 0 | 381 | 6110.611 | 6106.405 | 4 | 0 |
cvc5 | 0 | 381 | 6149.641 | 6150.29 | 4 | 0 |
z3-4.8.17n | 0 | 374 | 16728.08 | 16608.477 | 11 | 0 |
MathSATn | 0 | 132 | 3703.491 | 3704.244 | 3 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2021-SMTInterpoln | 0 | 382 | 4478.692 | 3256.564 | 2 | 0 |
smtinterpol | 0 | 382 | 4320.568 | 3261.826 | 2 | 0 |
Yices2 | 0 | 382 | 3631.731 | 3632.758 | 3 | 0 |
OpenSMT | 0 | 381 | 6112.101 | 6106.205 | 4 | 0 |
cvc5 | 0 | 381 | 6150.641 | 6150.19 | 4 | 0 |
z3-4.8.17n | 0 | 374 | 16728.08 | 16608.477 | 11 | 0 |
MathSATn | 0 | 132 | 3704.071 | 3704.174 | 3 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.