SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2022

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QF_RDL (Model Validation Track)

Competition results for the QF_RDL logic in the Model Validation Track.

Page generated on 2022-08-10 11:19:11 +0000

Benchmarks: 109
Time Limit: 1200 seconds
Memory Limit: 60 GB

Winners

Sequential PerformanceParallel Performance
Yices2Yices2

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreTimeout Memout
2021-Yices2 model-validationn 0 109 664.044 664.2130 0
Yices2 0 109 667.808 668.0080 0
cvc5 0 106 6097.676 6089.5093 0
MathSATn 0 105 6801.268 6788.7154 0
OpenSMT 0 103 15107.311 15110.896 0
z3-4.8.17n 0 102 11342.31 11336.0117 0
smtinterpol 0 101 14642.128 13740.2858 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreTimeout Memout
2021-Yices2 model-validationn 0 109664.044664.2130 0
Yices2 0 109667.808668.0080 0
cvc5 0 1066098.4666089.4193 0
MathSATn 0 1056801.5686788.5654 0
OpenSMT 0 10315108.17115110.626 0
z3-4.8.17n 0 10211343.4611335.7017 0
smtinterpol 0 10214643.13813721.8757 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.