The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_RDL logic in the Model Validation Track.
Page generated on 2022-08-10 11:19:11 +0000
Benchmarks: 109 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
Yices2 | Yices2 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2021-Yices2 model-validationn | 0 | 109 | 664.044 | 664.213 | 0 | 0 |
Yices2 | 0 | 109 | 667.808 | 668.008 | 0 | 0 |
cvc5 | 0 | 106 | 6097.676 | 6089.509 | 3 | 0 |
MathSATn | 0 | 105 | 6801.268 | 6788.715 | 4 | 0 |
OpenSMT | 0 | 103 | 15107.311 | 15110.89 | 6 | 0 |
z3-4.8.17n | 0 | 102 | 11342.31 | 11336.011 | 7 | 0 |
smtinterpol | 0 | 101 | 14642.128 | 13740.285 | 8 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2021-Yices2 model-validationn | 0 | 109 | 664.044 | 664.213 | 0 | 0 |
Yices2 | 0 | 109 | 667.808 | 668.008 | 0 | 0 |
cvc5 | 0 | 106 | 6098.466 | 6089.419 | 3 | 0 |
MathSATn | 0 | 105 | 6801.568 | 6788.565 | 4 | 0 |
OpenSMT | 0 | 103 | 15108.171 | 15110.62 | 6 | 0 |
z3-4.8.17n | 0 | 102 | 11343.46 | 11335.701 | 7 | 0 |
smtinterpol | 0 | 102 | 14643.138 | 13721.875 | 7 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.