The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_IDL logic in the Model Validation Track.
Page generated on 2022-08-10 11:19:11 +0000
Benchmarks: 743 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
Z3++ | Z3++ |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Z3++ | 0 | 684 | 109156.553 | 109164.919 | 59 | 0 |
z3-4.8.17n | 0 | 665 | 124573.695 | 124521.647 | 78 | 0 |
2020-z3n | 0 | 659 | 122753.515 | 122732.699 | 80 | 0 |
Yices2 | 0 | 651 | 127871.673 | 127859.163 | 92 | 0 |
OpenSMT | 0 | 596 | 231026.473 | 231049.39 | 147 | 0 |
cvc5 | 0 | 561 | 278768.105 | 278816.827 | 182 | 0 |
smtinterpol | 0 | 447 | 414564.584 | 408324.505 | 296 | 0 |
MathSATn | 0 | 426 | 401010.068 | 401049.32 | 305 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Z3++ | 0 | 684 | 109164.673 | 109162.539 | 59 | 0 |
z3-4.8.17n | 0 | 665 | 124580.575 | 124519.847 | 78 | 0 |
2020-z3n | 0 | 659 | 122765.975 | 122729.029 | 80 | 0 |
Yices2 | 0 | 651 | 127880.433 | 127856.383 | 92 | 0 |
OpenSMT | 0 | 596 | 231041.313 | 231043.77 | 147 | 0 |
cvc5 | 0 | 561 | 278809.665 | 278808.437 | 182 | 0 |
smtinterpol | 0 | 447 | 414564.584 | 408324.505 | 296 | 0 |
MathSATn | 0 | 426 | 401051.168 | 401037.8 | 305 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.