The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the LRA logic in the Incremental Track.
Page generated on 2022-08-10 11:18:21 +0000
Benchmarks: 5 Time Limit: 1200 seconds Memory Limit: 60 GB
Parallel Performance |
---|
cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
2021-cvc5-incn | 0 | 15969 | 78.167 | 70.128 | 0 | 0 | 0 |
cvc5 | 0 | 15969 | 175.935 | 174.621 | 0 | 0 | 0 |
UltimateEliminator+MathSAT | 0 | 15969 | 338.168 | 247.47 | 0 | 0 | 0 |
z3-4.8.17n | 0 | 13477 | 3602.584 | 3602.276 | 2492 | 3 | 0 |
smtinterpol | 0 | 12721 | 1262.598 | 1222.599 | 3248 | 1 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.