The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the BVFPLRA logic in the Incremental Track.
Page generated on 2022-08-10 11:18:21 +0000
Benchmarks: 9 Time Limit: 1200 seconds Memory Limit: 60 GB
| Parallel Performance | 
|---|
| Bitwuzla | 
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout | 
|---|---|---|---|---|---|---|---|
| Bitwuzla | 0 | 3144 | 7259.96 | 7260.028 | 2453 | 6 | 0 | 
| cvc5 | 0 | 2964 | 7228.827 | 7228.57 | 2633 | 6 | 0 | 
| UltimateEliminator+MathSAT | 0 | 2157 | 194.2 | 138.591 | 3440 | 0 | 0 | 
  
    n Non-competing.
  
    N/A: Benchmarks not known to be SAT/UNSAT, respectively.