SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

GitHub

Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions

SMT-COMP 2022

Rules
Benchmarks
Tools
Specs
Proof Exhibition Track
Parallel & Cloud Tracks
Participants
Results
Statistics
Comparisons
Slides

BV (Incremental Track)

Competition results for the BV logic in the Incremental Track.

Page generated on 2022-08-10 11:18:21 +0000

Benchmarks: 18
Time Limit: 1200 seconds
Memory Limit: 60 GB

Winners

Parallel Performance
cvc5

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
2019-Z3n 0 371717566.3667565.47216855 0
z3-4.8.17n 0 366466530.9346529.8522105 0
cvc5 0 358329532.3669529.82630247 0
Bitwuzla 0 3398412768.60212768.40948729 0
UltimateEliminator+MathSAT 0 189121520.2781367.432199441 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.