The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the ALIA division in the Single Query Track.
Page generated on 2020-07-04 11:46:58 +0000
Benchmarks: 19 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance | SAT Performance (parallel) | UNSAT Performance (parallel) | 24s Performance (parallel) |
---|---|---|---|---|
SMTInterpol | SMTInterpol | SMTInterpol | CVC4 | SMTInterpol |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|---|---|---|
2018-Z3n | 0 | 19 | 1.181 | 1.182 | 19 | 1 | 18 | 0 | 0 | 0 | |
z3n | 0 | 19 | 1.258 | 1.261 | 19 | 1 | 18 | 0 | 0 | 0 | |
SMTInterpol-fixedn | 0 | 19 | 152.058 | 61.997 | 19 | 1 | 18 | 0 | 0 | 0 | |
SMTInterpol | 0 | 19 | 154.548 | 62.481 | 19 | 1 | 18 | 0 | 0 | 0 | |
CVC4 | 0 | 18 | 3.189 | 3.191 | 18 | 0 | 18 | 1 | 0 | 0 | |
Alt-Ergo | 0 | 18 | 11.288 | 4.645 | 18 | 0 | 18 | 1 | 0 | 0 | |
Vampire | 0 | 15 | 5381.224 | 5090.651 | 15 | 0 | 15 | 4 | 4 | 0 | |
veriT | 0 | 4 | 17886.136 | 17889.305 | 4 | 0 | 4 | 15 | 14 | 0 | |
veriT+viten | 0 | 4 | 17998.358 | 18000.45 | 4 | 0 | 4 | 15 | 14 | 1 | |
UltimateEliminator+MathSAT | 0 | 0 | 15632.998 | 15621.177 | 0 | 0 | 0 | 19 | 13 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|---|---|---|
2018-Z3n | 0 | 19 | 1.181 | 1.182 | 19 | 1 | 18 | 0 | 0 | 0 | |
z3n | 0 | 19 | 1.258 | 1.261 | 19 | 1 | 18 | 0 | 0 | 0 | |
SMTInterpol-fixedn | 0 | 19 | 152.058 | 61.997 | 19 | 1 | 18 | 0 | 0 | 0 | |
SMTInterpol | 0 | 19 | 154.548 | 62.481 | 19 | 1 | 18 | 0 | 0 | 0 | |
CVC4 | 0 | 18 | 3.189 | 3.191 | 18 | 0 | 18 | 1 | 0 | 0 | |
Alt-Ergo | 0 | 18 | 11.288 | 4.645 | 18 | 0 | 18 | 1 | 0 | 0 | |
Vampire | 0 | 17 | 7771.684 | 3953.271 | 17 | 0 | 17 | 2 | 2 | 0 | |
veriT | 0 | 4 | 17888.316 | 17888.715 | 4 | 0 | 4 | 15 | 14 | 0 | |
veriT+viten | 0 | 4 | 18000.058 | 18000.06 | 4 | 0 | 4 | 15 | 14 | 1 | |
UltimateEliminator+MathSAT | 0 | 0 | 15632.998 | 15621.177 | 0 | 0 | 0 | 19 | 13 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|---|---|---|
z3n | 0 | 1 | 0.051 | 0.051 | 1 | 1 | 0 | 18 | 0 | 0 |
2018-Z3n | 0 | 1 | 0.054 | 0.054 | 1 | 1 | 0 | 18 | 0 | 0 |
SMTInterpol | 0 | 1 | 0.695 | 0.428 | 1 | 1 | 0 | 18 | 0 | 0 |
SMTInterpol-fixedn | 0 | 1 | 0.693 | 0.433 | 1 | 1 | 0 | 18 | 0 | 0 |
CVC4 | 0 | 0 | 0.289 | 0.296 | 0 | 0 | 0 | 19 | 0 | 0 |
Alt-Ergo | 0 | 0 | 1.148 | 0.434 | 0 | 0 | 0 | 19 | 0 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 3.452 | 2.441 | 0 | 0 | 0 | 19 | 13 | 0 |
veriT | 0 | 0 | 1088.25 | 1088.65 | 0 | 0 | 0 | 19 | 14 | 0 |
veriT+viten | 0 | 0 | 1200.0 | 1200.0 | 0 | 0 | 0 | 19 | 14 | 1 |
Vampire | 0 | 0 | 1200.0 | 1200.0 | 0 | 0 | 0 | 19 | 2 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|---|---|---|
2018-Z3n | 0 | 18 | 1.126 | 1.128 | 18 | 0 | 18 | 1 | 0 | 0 |
z3n | 0 | 18 | 1.208 | 1.21 | 18 | 0 | 18 | 1 | 0 | 0 |
CVC4 | 0 | 18 | 2.9 | 2.895 | 18 | 0 | 18 | 1 | 0 | 0 |
Alt-Ergo | 0 | 18 | 10.139 | 4.212 | 18 | 0 | 18 | 1 | 0 | 0 |
SMTInterpol-fixedn | 0 | 18 | 151.366 | 61.564 | 18 | 0 | 18 | 1 | 0 | 0 |
SMTInterpol | 0 | 18 | 153.853 | 62.053 | 18 | 0 | 18 | 1 | 0 | 0 |
Vampire | 0 | 17 | 6571.684 | 2753.271 | 17 | 0 | 17 | 2 | 2 | 0 |
veriT+viten | 0 | 4 | 16800.058 | 16800.06 | 4 | 0 | 4 | 15 | 14 | 1 |
veriT | 0 | 4 | 16800.066 | 16800.065 | 4 | 0 | 4 | 15 | 14 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 15629.546 | 15618.736 | 0 | 0 | 0 | 19 | 13 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Solved | Solved SAT | Solved UNSAT | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|---|---|---|
2018-Z3n | 0 | 19 | 1.181 | 1.182 | 19 | 1 | 18 | 0 | 0 | 0 | |
z3n | 0 | 19 | 1.258 | 1.261 | 19 | 1 | 18 | 0 | 0 | 0 | |
SMTInterpol-fixedn | 0 | 19 | 152.058 | 61.997 | 19 | 1 | 18 | 0 | 0 | 0 | |
SMTInterpol | 0 | 19 | 154.548 | 62.481 | 19 | 1 | 18 | 0 | 0 | 0 | |
CVC4 | 0 | 18 | 3.189 | 3.191 | 18 | 0 | 18 | 1 | 0 | 0 | |
Alt-Ergo | 0 | 18 | 11.288 | 4.645 | 18 | 0 | 18 | 1 | 0 | 0 | |
Vampire | 0 | 7 | 301.916 | 295.424 | 7 | 0 | 7 | 12 | 12 | 0 | |
veriT+viten | 0 | 4 | 360.058 | 360.06 | 4 | 0 | 4 | 15 | 14 | 1 | |
veriT | 0 | 4 | 360.066 | 360.065 | 4 | 0 | 4 | 15 | 15 | 0 | |
UltimateEliminator+MathSAT | 0 | 0 | 344.998 | 333.177 | 0 | 0 | 0 | 19 | 13 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.