The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFLRA logic in the Unsat Core Track.
Page generated on 2023-07-06 16:05:43 +0000
Benchmarks: 10 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance |
|---|---|
| cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-cvc5-ucn | 0 | 16 | 0.2 | 0.196 | 0 | 0 |
| cvc5 | 0 | 16 | 0.214 | 0.21 | 0 | 0 |
| SMTInterpol | 0 | 16 | 7.043 | 4.723 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 0.0 | 0.0 | 0 | 0 |
| Vampire | 0 | 0 | 7.008 | 2.671 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-cvc5-ucn | 0 | 16 | 0.2 | 0.196 | 0 | 0 |
| cvc5 | 0 | 16 | 0.214 | 0.21 | 0 | 0 |
| SMTInterpol | 0 | 16 | 7.043 | 4.723 | 0 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 0.0 | 0.0 | 0 | 0 |
| Vampire | 0 | 0 | 7.008 | 2.671 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.