The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFLRA logic in the Incremental Track.
Page generated on 2023-07-06 16:05:24 +0000
Benchmarks: 935 Time Limit: 1200 seconds Memory Limit: 60 GB
Parallel Performance |
---|
cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
2021-z3n | 0 | 355479 | 145890.98 | 145946.59 | 208900 | 58 | 0 |
cvc5 | 0 | 121424 | 41745.62 | 41790.46 | 442955 | 17 | 0 |
SMTInterpol | 0 | 115741 | 237060.81 | 226499.74 | 448638 | 215 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 0.0 | 0.0 | 564379 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.