The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFIDL logic in the Unsat Core Track.
Page generated on 2023-07-06 16:05:43 +0000
Benchmarks: 30 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
cvc5 | cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2021-cvc5-ucn | 0 | 1916 | 1.992 | 1.988 | 0 | 0 |
cvc5 | 0 | 1913 | 1.965 | 1.952 | 0 | 0 |
SMTInterpol | 0 | 983 | 56.661 | 28.443 | 3 | 0 |
Vampire | 0 | 459 | 1.316 | 1.337 | 2 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 0.0 | 0.0 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
2021-cvc5-ucn | 0 | 1916 | 1.992 | 1.988 | 0 | 0 |
cvc5 | 0 | 1913 | 1.965 | 1.952 | 0 | 0 |
SMTInterpol | 0 | 983 | 56.661 | 28.443 | 3 | 0 |
Vampire | 0 | 459 | 1.316 | 1.337 | 2 | 0 |
UltimateEliminator+MathSAT | 0 | 0 | 0.0 | 0.0 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.