The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFLRA logic in the Model Validation Track.
Page generated on 2023-07-06 16:06:00 +0000
Benchmarks: 385 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
Yices2 | Yices2 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Yices2 | 0 | 383 | 535.614 | 536.189 | 2 | 0 |
SMTInterpol | 0 | 383 | 2280.009 | 1023.769 | 2 | 0 |
2022-smtinterpoln | 0 | 383 | 2467.184 | 1108.121 | 2 | 0 |
cvc5 | 0 | 382 | 2339.695 | 2338.192 | 3 | 0 |
OpenSMT | 0 | 378 | 999.489 | 998.831 | 7 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Yices2 | 0 | 383 | 535.614 | 536.189 | 2 | 0 |
SMTInterpol | 0 | 383 | 2280.009 | 1023.769 | 2 | 0 |
2022-smtinterpoln | 0 | 383 | 2467.184 | 1108.121 | 2 | 0 |
cvc5 | 0 | 382 | 2339.695 | 2338.192 | 3 | 0 |
OpenSMT | 0 | 378 | 999.489 | 998.831 | 7 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.