The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFIDL logic in the Model Validation Track.
Page generated on 2023-07-06 16:06:00 +0000
Benchmarks: 206 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
OpenSMT | OpenSMT |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
OpenSMT | 0 | 199 | 8353.109 | 8354.332 | 7 | 0 |
2022-smtinterpoln | 0 | 197 | 11652.325 | 10079.556 | 9 | 0 |
SMTInterpol | 0 | 182 | 16070.774 | 14662.571 | 24 | 0 |
cvc5 | 0 | 169 | 25679.498 | 25684.502 | 37 | 0 |
Yices2 | 0 | 141 | 16968.849 | 16969.52 | 65 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
OpenSMT | 0 | 199 | 8353.109 | 8354.332 | 7 | 0 |
2022-smtinterpoln | 0 | 197 | 11652.325 | 10079.556 | 9 | 0 |
SMTInterpol | 0 | 183 | 17312.494 | 15836.461 | 23 | 0 |
cvc5 | 0 | 169 | 25679.498 | 25684.502 | 37 | 0 |
Yices2 | 0 | 141 | 16968.849 | 16969.52 | 65 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.