The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UF logic in the Model Validation Track.
Page generated on 2023-07-06 16:06:00 +0000
Benchmarks: 1571 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance |
|---|---|
| Yices2 | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-Yices2 model-validationn | 0 | 1571 | 67.859 | 70.124 | 0 | 0 |
| 2022-Yices2n | 0 | 1571 | 67.877 | 70.128 | 0 | 0 |
| Yices2 | 0 | 1571 | 68.695 | 70.91 | 0 | 0 |
| OpenSMT | 0 | 1571 | 260.241 | 269.546 | 0 | 0 |
| cvc5 | 0 | 1571 | 459.001 | 453.626 | 0 | 0 |
| SMTInterpol | 0 | 1571 | 4261.414 | 1700.092 | 0 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| 2021-Yices2 model-validationn | 0 | 1571 | 67.859 | 70.124 | 0 | 0 |
| 2022-Yices2n | 0 | 1571 | 67.877 | 70.128 | 0 | 0 |
| Yices2 | 0 | 1571 | 68.695 | 70.91 | 0 | 0 |
| OpenSMT | 0 | 1571 | 260.241 | 269.546 | 0 | 0 |
| cvc5 | 0 | 1571 | 459.001 | 453.626 | 0 | 0 |
| SMTInterpol | 0 | 1571 | 4261.414 | 1700.092 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.