The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_RDL logic in the Model Validation Track.
Page generated on 2023-07-06 16:06:00 +0000
Benchmarks: 110 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance |
|---|---|
| Yices2 | Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| Yices2 | 0 | 110 | 1727.632 | 1727.834 | 0 | 0 |
| cvc5 | 0 | 107 | 3277.809 | 3254.38 | 3 | 0 |
| 2022-OpenSMTn | 0 | 104 | 9603.394 | 9580.32 | 6 | 0 |
| OpenSMT | 0 | 103 | 8255.606 | 8253.526 | 7 | 0 |
| SMTInterpol | 0 | 102 | 5613.849 | 4654.118 | 8 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| Yices2 | 0 | 110 | 1727.632 | 1727.834 | 0 | 0 |
| cvc5 | 0 | 107 | 3277.809 | 3254.38 | 3 | 0 |
| 2022-OpenSMTn | 0 | 104 | 9603.394 | 9580.32 | 6 | 0 |
| OpenSMT | 0 | 103 | 8255.606 | 8253.526 | 7 | 0 |
| SMTInterpol | 0 | 102 | 5613.849 | 4654.118 | 8 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.