The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_LIRA logic in the Model Validation Track.
Page generated on 2023-07-06 16:06:00 +0000
Benchmarks: 1 Time Limit: 1200 seconds Memory Limit: 60 GB
Sequential Performance | Parallel Performance |
---|---|
Yices2 | Yices2 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Yices2 | 0 | 1 | 0.11 | 0.11 | 0 | 0 |
cvc5 | 0 | 1 | 2.712 | 2.719 | 0 | 0 |
SMTInterpol | 0 | 1 | 21.739 | 8.719 | 0 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
---|---|---|---|---|---|---|
Yices2 | 0 | 1 | 0.11 | 0.11 | 0 | 0 |
cvc5 | 0 | 1 | 2.712 | 2.719 | 0 | 0 |
SMTInterpol | 0 | 1 | 21.739 | 8.719 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.