The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_LIA logic in the Model Validation Track.
Page generated on 2023-07-06 16:06:00 +0000
Benchmarks: 4212 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance | 
|---|---|
| Z3++ | Z3++ | 
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout | 
|---|---|---|---|---|---|---|
| Z3++ | 0 | 4079 | 69474.705 | 69269.424 | 118 | 8 | 
| 2022-Z3++n | 0 | 4078 | 67971.653 | 67776.922 | 118 | 8 | 
| OpenSMT | 0 | 4006 | 210164.737 | 210197.138 | 205 | 0 | 
| cvc5 | 0 | 3999 | 96508.925 | 96349.56 | 213 | 0 | 
| Yices2 | 0 | 3913 | 61708.648 | 61623.772 | 299 | 0 | 
| SMTInterpol | 0 | 3822 | 150971.875 | 127443.04 | 390 | 0 | 
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout | 
|---|---|---|---|---|---|---|
| Z3++ | 0 | 4079 | 69474.705 | 69269.424 | 118 | 8 | 
| 2022-Z3++n | 0 | 4078 | 67971.653 | 67776.922 | 118 | 8 | 
| OpenSMT | 0 | 4006 | 210164.737 | 210197.138 | 205 | 0 | 
| cvc5 | 0 | 3999 | 96508.925 | 96349.56 | 213 | 0 | 
| Yices2 | 0 | 3913 | 61708.648 | 61623.772 | 299 | 0 | 
| SMTInterpol | 0 | 3822 | 150971.875 | 127443.04 | 390 | 0 | 
  
    n Non-competing.
  
    N/A: Benchmarks not known to be SAT/UNSAT, respectively.