The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_Equality+Bitvec division in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 1389 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics: This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 1203 | 55146.418 | 54718.315 | 186 | 0 | 182 | 4 |
cvc5 | 0 | 796 | 1637.051 | 1590.797 | 593 | 0 | 563 | 4 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 1203 | 55146.418 | 54718.315 | 186 | 0 | 182 | 4 |
cvc5 | 0 | 796 | 1637.051 | 1590.797 | 593 | 0 | 563 | 4 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.