The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFBVDT logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 6 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| cvc5-lfsc | 0 | 3 | 554.871 | 554.487 | 3 | 0 | 3 |
| cvc5 | 0 | 0 | 0.0 | 0.0 | 6 | 3 | 3 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| cvc5-lfsc | 0 | 3 | 554.871 | 554.487 | 3 | 0 | 3 |
| cvc5 | 0 | 0 | 0.0 | 0.0 | 6 | 3 | 3 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.