The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the QF_Equality+Bitvec+Arith division in the Incremental Track.
Page generated on 2023-07-06 16:05:24 +0000
Benchmarks: 523 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics:Parallel Performance |
---|
cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
Yices2 Fixedn | 0 | 817 | 5336.44 | 5359.19 | 17 | 0 | 17 | 0 |
cvc5 | 0 | 761 | 24823.51 | 24860.0 | 73 | 0 | 73 | 0 |
Yices2 | 1 | 817 | 5868.86 | 5891.01 | 17 | 0 | 16 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.