The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_UFBVLIA logic in the Incremental Track.
Page generated on 2023-07-06 16:05:24 +0000
Benchmarks: 179 Time Limit: 1200 seconds Memory Limit: 60 GB
| Parallel Performance |
|---|
| Yices2 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| Yices2 Fixedn | 0 | 207 | 6.48 | 12.31 | 0 | 0 | 0 |
| Yices2 | 0 | 207 | 6.53 | 12.54 | 0 | 0 | 0 |
| cvc5 | 0 | 207 | 39.0 | 57.4 | 0 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.