The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the QF_Array+Bitvec+LinArith division in the Model Validation Track.
Page generated on 2023-06-27 14:59:09 +0000
Benchmarks: 5924 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics:
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 5450 | 141835.535 | 141768.53 | 462 | 1 | |
Bitwuzla Fixedn | 0 | 5213 | 7751.025 | 7790.875 | 3 | 0 | |
Bitwuzla | 0 | 5213 | 7765.231 | 7812.831 | 3 | 0 | |
SMTInterpol | 0 | 670 | 3980.451 | 3060.965 | 0 | 0 | |
Yices2 | 0 | 39 | 2599.383 | 2600.302 | 20 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5 | 0 | 5450 | 141835.535 | 141768.53 | 462 | 1 | |
Bitwuzla Fixedn | 0 | 5213 | 7751.025 | 7790.875 | 3 | 0 | |
Bitwuzla | 0 | 5213 | 7765.231 | 7812.831 | 3 | 0 | |
SMTInterpol | 0 | 670 | 3980.451 | 3060.965 | 0 | 0 | |
Yices2 | 0 | 39 | 2599.383 | 2600.302 | 20 | 0 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.