The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the LRA logic in the Incremental Track.
Page generated on 2023-07-06 16:05:24 +0000
Benchmarks: 5 Time Limit: 1200 seconds Memory Limit: 60 GB
Parallel Performance |
---|
cvc5 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
2021-cvc5-incn | 0 | 15969 | 72.27 | 72.11 | 0 | 0 | 0 |
cvc5 | 0 | 15969 | 143.3 | 143.17 | 0 | 0 | 0 |
UltimateEliminator+MathSAT | 0 | 15969 | 418.59 | 322.38 | 0 | 0 | 0 |
SMTInterpol | 0 | 12723 | 119.49 | 54.22 | 3246 | 1 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.