The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the LIA logic in the Unsat Core Track.
Page generated on 2023-07-06 16:05:43 +0000
Benchmarks: 227 Time Limit: 1200 seconds Memory Limit: 60 GB
| Sequential Performance | Parallel Performance |
|---|---|
| cvc5 | cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| cvc5 | 0 | 7 | 12.141 | 12.037 | 1 | 0 |
| 2022-cvc5n | 0 | 7 | 19.635 | 19.604 | 1 | 0 |
| Vampire | 0 | 0 | 57.643 | 28.509 | 1 | 0 |
| SMTInterpol | 0 | 0 | 114.964 | 78.283 | 18 | 0 |
| UltimateEliminator+MathSAT | 1 | 6 | 2838.519 | 1910.692 | 3 | 0 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Timeout | Memout |
|---|---|---|---|---|---|---|
| cvc5 | 0 | 7 | 12.141 | 12.037 | 1 | 0 |
| 2022-cvc5n | 0 | 7 | 19.635 | 19.604 | 1 | 0 |
| Vampire | 0 | 0 | 57.643 | 28.509 | 1 | 0 |
| SMTInterpol | 0 | 0 | 114.964 | 78.283 | 18 | 0 |
| UltimateEliminator+MathSAT | 1 | 6 | 2838.519 | 1910.692 | 3 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.