The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the Equality+MachineArith division in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 2006 Time Limit: 1200 seconds Memory Limit: 60 GB
Logics:
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 621 | 23411.704 | 23380.813 | 1385 | 0 | 459 | 198 |
cvc5 | 0 | 387 | 2190.448 | 2156.983 | 1619 | 0 | 692 | 196 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Abstained | Timeout | Memout |
---|---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 621 | 23411.704 | 23380.813 | 1385 | 0 | 459 | 198 |
cvc5 | 0 | 387 | 2190.448 | 2156.983 | 1619 | 0 | 692 | 196 |
n Non-competing.
Abstained: Total of benchmarks in logics in this division that solver chose to abstain from. For SAT/UNSAT scores, this column also includes benchmarks not known to be SAT/UNSAT.