SMT-COMP

The International Satisfiability Modulo Theories (SMT) Competition.

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SMT-COMP 2023

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Model Validation Track
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AUFBVDTLIA (Proof Exhibition Track)

Competition results for the AUFBVDTLIA logic in the Proof Exhibition Track.

Page generated on 2023-07-06 16:06:18 +0000

Benchmarks: 185
Time Limit: 1200 seconds
Memory Limit: 60 GB

This track is experimental. Solvers are only ranked by performance, but no winner is selected.

Sequential Performance

Solver Error Score Correct Score CPU Time Score Wall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 121 968.364 967.2946464 0
cvc5 0 100 583.557 574.2758583 0

Parallel Performance

Solver Error Score Correct ScoreCPU Time ScoreWall Time ScoreUnsolvedTimeout Memout
cvc5-lfsc 0 121968.364967.2946464 0
cvc5 0 100583.557574.2758583 0

n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.