The International Satisfiability Modulo Theories (SMT) Competition.
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Competition results for the UFBV logic in the Proof Exhibition Track.
Page generated on 2023-07-06 16:06:18 +0000
Benchmarks: 127 Time Limit: 1200 seconds Memory Limit: 60 GB
This track is experimental. Solvers are only ranked by performance, but no winner is selected.
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 69 | 6812.278 | 6811.977 | 58 | 10 | 0 |
cvc5 | 0 | 27 | 642.159 | 628.5 | 100 | 47 | 0 |
Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
---|---|---|---|---|---|---|---|
cvc5-lfsc | 0 | 69 | 6812.278 | 6811.977 | 58 | 10 | 0 |
cvc5 | 0 | 27 | 642.159 | 628.5 | 100 | 47 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.