The International Satisfiability Modulo Theories (SMT) Competition.
Home
Introduction
Benchmark Submission
Publications
SMT-LIB
Previous Editions
Competition results for the AUFNIRA logic in the Incremental Track.
Page generated on 2023-07-06 16:05:23 +0000
Benchmarks: 165 Time Limit: 1200 seconds Memory Limit: 60 GB
| Parallel Performance |
|---|
| cvc5 |
| Solver | Error Score | Correct Score | CPU Time Score | Wall Time Score | Unsolved | Timeout | Memout |
|---|---|---|---|---|---|---|---|
| cvc5 | 0 | 3042 | 1331.2 | 1353.29 | 410 | 27 | 0 |
| 2022-z3-4.8.17n | 0 | 2752 | 6240.76 | 6257.07 | 700 | 34 | 0 |
| UltimateEliminator+MathSAT | 0 | 0 | 0.0 | 0.0 | 3452 | 0 | 0 |
| SMTInterpol | 0 | 0 | 0.0 | 0.0 | 3452 | 0 | 0 |
n Non-competing.
N/A: Benchmarks not known to be SAT/UNSAT, respectively.